1 semiconductor description the HC-55564 is a half duplex modulator/demodulator cmos intergrated circuit used to convert voice signals into serial nrz digital data and to reconvert that data into voice. the conver- sion is by delta-modulation, using the continuously variable slope (cvsd) method of modulation/demodulation. while the signals are compatible with other cvsd circuits, the inter- nal design is unique. the analog loop filters have been replaced by very low power digital filters which require no external timing compo- nents. this approach allows inclusion of many desirable features which would be difficult to implement using other approaches. the fundamental advantages of delta-modulation, along with its simplicity and serial data format, provide an ef?cient (low data rate/low memory requirements) method for voice digitization. the HC-55564 is usable from 9kbits/s to above 64kbps. see the harris military databook for a mil-std-883c compliant cvsd. application note 607. ordering information part number temp. range ( o c) package pkg. no. hc1-55564-2 -55 to 125 14 ld cerdip f14.3 hc1-55564-5 0 to 75 14 ld cerdip f14.3 hc1-55564-9 -40 to 85 14 ld cerdip f14.3 hc3-55564-5 0 to 75 14 ld pdip e14.3 hc9p55564-5 0 to 75 16 ld plastic soic (w) m16.3 features ? all digital ? requires few external parts ? low power drain: 1.5mw typical from single 4.5v to 6v supply ? time constants determined by clock frequency; no calibration or drift problems: automatic offset adjustment ? half duplex operation under digital control ? filter reset under digital control ? automatic overload recovery ? automatic quiet pattern generation ? agc control signal available applications ? voice transmission over data channels (modems) ? voice/data multiplexing (pair gain) ? voice encryption/scrambling ? voicemail ? audio manipulations: delay lines, time compression, echo generation/suppression, special effects, etc. ? pagers/satellites ? data acquisition systems ? voice i/o for digital systems and speech synthesis requiring small size, low weight, and ease of reprogrammability ? related literature - an607, delta modulation for voice transmission february 1999 pinouts HC-55564 (pdip, cerdip) top view HC-55564 (soic) top view v dd analog gnd a out a gc a in nc nc dig out fz dig in apt enc/dec clock dig gnd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 v dd analog gnd a out a gc ain nc nc nc dig out dig in apt enc/dec clock dig gnd nc fz caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? harris corporation 1999 low bit rate voiceband encoders/decoder HC-55564 continuously variable slope delta-modulator (cvsd) file number 2889.5 [ /title (hc- 55564 ) / sub- j ect (con- tinu- ously vari- able slope delta- modu- lator (cvs d)) / autho r () / key- words (har- ris semi- con- ductor , tele- com, slics , slac s, tele- phone, tele- phony, obsolete product no recommended repla cement call central applications 1-800-442-7747 or email: centapp@harris.com
2 HC-55564 absolute maximum ratings thermal information voltage at any pin . . . . . . . . . . . . . . . . . . . .gnd -0.3v to v dd 0.3v maximum v dd voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0v junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 o c operating conditions temperature range HC-55564-5, -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 0 c HC-55564-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 0 c HC-55564-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 0 c operating v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 6.0v thermal resistance (typical, note 1) q ja ( o c/w) cerdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 maximum junction temperature (plastic package) . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c die characteristics transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897 die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 x 82 substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v dd process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bimose caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations unless otherwise speci?ed, typical parameters are at 25 o c, min-max are over operating temperature ranges. v dd = 5.0v, sampling rate = 16kbps, ag = dg = 0v, a in = 1.2v rms parameter symbol conditions min typ max units sampling rate clk note 2 9 16 64 kbps supply current i dd - 0.3 1.5 ma logic 1 input v ih note 3 3.5 - - v logic 0 input v il note 3 - - 1.5 v logic 1 output v oh note 4 4.0 - - v logic 0 output v ol note 4 - - 0.4 v clock duty cycle 30 - 70 % audio input voltage a in ac coupled (note 5) - 0.5 1.2 v rms audio output voltage a out ac coupled (note 6) - 0.5 1.2 v rms audio input impedance z in note 7 - 280 - k w audio output impedance z out note 7 - 150 - k w transfer gain a e-d no load, audio in to audio out. -2.0 - +2.0 db syllabic filter time constant t sf note 8 - 4.0 - ms signal estimate filter time constant t se note 8 1.0 - - ms enc threshold ain at 100hz (note 9), (typ) 0.3% = 15mv rms -6-mv peak minimum step size mss note 10 - 0.1 - %v dd quieting pattern amplitude v qp fz = 0v or apt = 0v (note 11) - 10 - mv p-p agc threshold v at h note 12 - 0.1 - f.s. clamping threshold v cth note 13 - 0.75 - f.s. notes: 2. there is one nrz (non-return zero) data bit per clock period. data is clocked out on the negative clock edge. data is clocked into the cvsd on the positive going edge (see figure 2). clock may be run at less than 9kbps and greater than 64kbps. 3. logic inputs are cmos compatible at supply voltage and are diode protected. digital data input is nrz at clock rate. 4. logic outputs are cmos compatible at supply voltage and will withstand short-circuits to v dd or ground. digital data output is nrz and changes with negative clock transitions. each output will drive one ls ttl load. 5. recommended voice input range for best voice performance. should be externally ac coupled. 6. may be used for side-tone in encode mode. should be externally ac coupled. varies with audio input level by 2db. 7. presents series impedance with audio signal. zero signal reference is approximately v dd /2. 8. note that filter time constants are inversely proportional to clock rate. both filters approximate single pole responses. 9. the minimum audio input voltage above which encoding takes place. 10. the minimum audio output voltage change that can be produced by the internal dac. 11. settled value, the quieting pattern or idle-channel audio output steps at one-half the bit rate, changing state on negative clock transitions. 12. a logic 0 will appear at the agc output pin when the recovered signal reaches one-half of full-scale value (positive or negative), i.e., at v dd /2 25% of v dd . 13. the recovered signal will be clamped, and the computation will be inhibited, when the recovered signal reaches three-quarter s of full- scale value, and will unclamp when it falls below this value (positive or negative).
3 HC-55564 functional diagram (dip pin numbers shown) pin descriptions pin number 14 lead dip symbol description 1v dd positive supply voltage. voltage range is 4.5v to 6.0v. 2 analog gnd analog ground connection to d/a ladders and comparator. 3a out audio out recovered from 10-bit dac. may be used as side tone at the transmitter. presents approximately 150k w source with dc offset of v dd /2. within 2db of audio input. should be ex- ternally ac coupled. 4 a gc automatic gain control output. a logic low level will appear at this output when the recovered signal excursion reaches one-half of full scale value. in each half cycle full scale is v dd /2. the mark-space ratio is proportional to the average signal level. 5a in audio input to comparator. should be externally ac coupled. presents approximately 280k w in series with v dd /2. 6, 7 nc no internal connection is made to these pins. 8 digital gnd logic ground. 0v reference for all logic inputs and outputs. 9 clock sampling rate clock. in the decode mode, must be synchronized with the digital input data such that the data is valid at the positive clock transition. in the encode mode, the digital data is clocked out on the negative going clock transition. the clock rate equals the data rate. 10 encode/ decode a single cvsd can provide half-duplex operation. the encode or decode function is selected by the logic level applied to this input. a low level selects the encode mode, a high level the decode mode. 11 apt alternate plain text input. activating this input caused a digital quieting pattern to be transmitted, how- ever; internally the cvsd is still functional and a signal is still available at the a out port. active low. 12 digital in input for the received digital nrz data. 13 fz force zero input. activating this input resets the internal logic and forces the digital output and the recovered audio output into the quieting condition. an alternating 1-0 pattern appears at the digital output at 1/2 the clock rate. when this is decoded by a receive cvsd, a 10mv p-p inaudible signal appears at audio output. active low. 14 digital out output for transmitted digital nrz data. note: 14. no active input should be left in a floating condition. 3 bit shift step size syllabic filter 4ms register logic digital modulator 1 signal estimate filter 1msec 10 bit dac apt (14) digital out f/f reset 6 z out 10 d t reset 10 bit dac 10 (3) a out (side tone) (4) a gc out q reset force zer o (9) digital gnd (10) enc/dec (11) (13) clock (8) (12) digital (1) v dd 3v to 6v z in analog gnd (2) (5) a in v dd 2 comparator in
4 HC-55564 timing waveforms figure 2. cvsd timing diagram 0 1 10 sampling clock fz/ apt dec/ enc digital nrz in digital nrz out t ds 01 1 t ds : data set up time 100ns typical cvsd hookup for evaluation the circuit in figure 3 is suf?cient to evaluate the voice qual- ity of the cvsd, since when encoding, the feedback signal at the audio output pin is the reconstructed audio input signal. cvsd design considerations are as follows: 1. care should be taken in layout to maintain isolation between analog and digital signal paths for proper noise consideration. 2. power supply decoupling is necessary as close to the device as possible. a 0.1 m f should be suf?cient. 3. ground, then power, must be present before any input sig- nals are applied to the cvsd. failure to observe this may cause a latchup condition which may be destructive. latchup may be removed by cycling the power off/on. a power-up reset circuit may be used that strobes force zero (pin 13) during power-up as follows: 4. analog (signal) ground (pin 2) should be externally tied to digital gnd (pin 8) and power supply ground. it is recom- mended that the a in and a out ground returns connect only to pin 2. 5. digital inputs and outputs are compatible with standard cmos logic using the same supply voltage. all unused logic inputs must be tied to the appropriate logic level for desired operation. it is recommended that unused inputs tied high be done so through a pull-up resistor (1k w to 10k w ). ttl outputs will require 1k w pull-up resistors. pins 4 and 14 will each drive cmos logic or one low power ttl input. 6. since the audio out pins are internally dc biased to v dd /2, ac coupling is required. in general, a value of 0.1 m f is suffi- cient for ac coupling of the cvsd audio pins to a filter circuit. 7. the agc output may be externally integrated to drive an agc pre-amp, or it could drive an led indicator through a buffer to indicate proper speaking volume. v dd r c (13) fz interface circuit for HC-55564 cvsd (dip pin numbers shown) audio source input level adjust r c r a , r b , c a optional r a c a r b vf x 1+ vf x 1- gs x vf r 0 pwri v cc v bb gndd clk pdn clk0 vf r i vf x 0 pwr0+ audio out tp3040 HC-55564 clk gen external control digital gnd analog gnd v dd a out a in agc d out d in fz apt e/d (to data i/f) (from data i/f) external control clk gnda 1 2 3 4 9 8 5v -5v 0.1 m 0.1 m 15 12 0.1 m 0.1 m 5 3 1 r d (note) 11 13 14 10 16 6 0.1 m 8 ? n 9 2 10 11 13 12 14 4 note: r d = 100k w to 1m w 5
5 HC-55564 figures 4, 5, and 6 illustrate the typical frequency response of the HC-55564 for varying input levels and for varying sampling rates. to prevent slope overload (slew limiting), the 0db boundary should not be exceeded. the frequency response is directly proportional to the sampling clock rate. the flat bandwidth at 0db doubles for every doubling in sampling rate. the output levels were mea- sured in the encode mode, without filtering, from a in to a out , at v dd = 5v. 0db = 1.2v rms . figure 4. 16kbps figure 5. 32kbps figure 6. 64kbps input frequency at a in (hz) a out -36db -30db -24db -18db -12db -6db 0db = input signal level 100 1000 -40 -30 -20 -10 db 10000 a in input frequency at a in (hz) 100 1000 -40 -30 -20 -10 db 10000 a out a in -36db -30db -24db -18db -12db -6db 0db = input signal level input frequency at a in (hz) 100 1000 -40 -30 -20 -10 db 10000 -36db -30db -24db -18db -12db -6db 0db = input signal level a out a in
6 HC-55564 the following typical performance distortion graphs were realized with the test con?guration of figure 7. the measurement vehicle for total harmonic distortion (thd) was an hp-339a distortion measurement set, and for 2nd and 3rd harmonic distortion, an hp-3582a spectrum analyzer. all measurement conditions were at v dd = 5v, and 2nd and 3rd harmonic distortion measurements were c- message ?ltered. 0db = 1.2v rms . figure 7. test and measurement circuit figure 8. cvsd signal level vs total harmonic distortion figure 9a. figure 10a. figure 9b. figure 10b. figure 9c. figure 9. cvsd input level vs 2nd and 3rd harmonic distortion figure 10c. figure 10. cvsd input frequency vs 2nd and 3rd harmonic distortion funct. 0.33 m f 5 HC-55564 a in a out dec/ enc v dd apt fz agnd dgnd 5v +1.0 m f c-mes- filter hp3582a spectrum analyzer or hp339a distortion analyzer gen. 0.33 m f sage 1 11 13 3 10 8 2 30% 10% 3% 1% -10 -20 -30 -40 -24 -16 -8 0 16khz 32khz 64khz input freq. = 1khz thd input signal level (db) (db) 16khz clock input frequency 1khz -10 -20 -30 -40 -24 -17 -11 input signal level (db) cvsd input level vs 2nd and 3rd harmonic distortion c-message weighted -50 db -3.8 +3.0 3rd 2nd input frequency (hz) -10 -20 -30 -40 0 1000 2000 cvsd signal to 2nd and 3rd harmonic distortion c-message weighted -50 db 3000 3rd 2nd v in = 0.5v rms 16khz clock -10 -20 -30 -40 -24 -17 -11 input signal level (db) cvsd input level vs 2nd and 3rd harmonic distortion c-message weighted -50 db -3.8 +3.0 3rd 2nd 32khz clock input frequency 1khz -10 -20 -30 -40 0 1000 2000 input frequency (hz) cvsd signal to 2nd and 3rd harmonic distortion c-message weighted -50 db 3000 3rd 2nd v in = 0.5v rms 32khz clock 4000 -60 -10 -20 -30 -40 -24 -17 -11 input signal level (db) cvsd input level vs 2nd and 3rd harmonic distortion c-message weighted -50 db -3.8 +3.0 3rd 2nd 64khz clock input frequency 1khz -10 -20 -30 -40 0 1000 2000 input frequency (hz) cvsd signal to 2nd and 3rd harmonic distortion c-message weighted -60 db 3000 3rd 2nd v in = 0.5v rms 64khz clock 4000 -50
7 HC-55564 ceramic dual-in-line frit seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this configuration dimension b3 replaces dimension b2. 5. this dimension allows for off-center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- a d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa c a - b m d s s e a f14.3 mil-std-1835 gdip1-t14 (d-1, configuration a) 14 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 a 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n14 148 rev. 0 4/94
8 HC-55564 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b 0.010 (0.25) c a m b s e d d1 a a2 l a1 -a- notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the mo series symbol list in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpen- dicular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e14.3 (jedec ms-001-aa issue d) 14 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n14 149 rev. 0 12/93
9 HC-55564 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m a notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m16.3 (jedec ms-013-aa issue c) 16 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.3977 0.4133 10.10 10.50 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n16 167 a 0 o 8 o 0 o 8 o - rev. 0 12/93
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